Four-person answering machine design 1. Design tasks and requirements: (1) Design a four-person answering machine for competition answering; ① There are multiple answering stations, and the number of answering machines is 8; ② Have the ability to Sierra Leoneans Escort There will be a 20-second countdown after the answering starts. After the 20-second countdown, if no one answers, it will display a timeout and alarm; ③ Can display the advanced answering station number and display a foul alarm; ( 2) After the system is reset, it enters the answering state. When one of the answering buttons is pressed, the answering electronic signal of that channel will turn off the other answering electronic signals, and the ring tone will sound at the same time. Until the button of that channel is released, the display board will show the answering station of that channel. No.; (3) Use VHDL language to design a four-person answering machine that meets the above performance requirements, and use a hierarchical design method to design the circuit; Sierra Leoneans Sugardaddy (4) After completing the entire design of the circuit, verify the correctness of the design topic through the system test box download. 2. Design ideas Design production Sierra Leoneans Escort A competition answering machine, each group is controlled by a answering switch, respectively S1, S2, S3, S4, low level indicates that the response is valid; the host control key K is set to control the entire system to clear 0 and the response to be valid. When the reset key is pressed, K=0, the system is cleared; when the reset key is lifted, K=1, the response starts; the system has the first response electronic signal identification and latch function. After the host resets the system and starts the response effectively, the first responder presses the response button and the corresponding output pin is connected to low potential 0. The circuit should remember the group of the first responder and turn off the other groups. button, that is, any other group of buttons will not cause the circuit to respond; the system prompts the first responder in two ways: one is to display its group name through a decoding program; the other is when the first responder is generated, Buzzer warning; set up the illegal circuit unit, when the responder presses the reset reset button before the host presses the reset button When the answer button is pressed, an illegal electronic signal is given as a high level. The white electronic signal light in the corresponding group lights up; when no one answers after the 20-second countdown, the timeout is displayed and the alarm is issued. The system design block diagram is shown in Figure 1. SL Escorts Figure 1 Overall design block diagram 3. VHDL program completion 1. Normal answering program and simulation This module includes the normal answering first electronic signal to identify and display the answering station number, and generate a sound reminder . Among them, S1, S2, S3, and S4 are the response buttons. When the corresponding button electronic signal is 0, there is a response electronic signal; K is the host button, press the reset button Sierra Leone Sugar When K, K=0, the system is cleared; when the reset button is raised, K=1, the response starts; G is the alarm electronic signal. Its VHDL source program is as follows: library ieee;use ieee.std_logic_1164.alSierra Leoneans Sugardaddyl;use ieee. std_logic_arith.SL Escortsall;use ieee. std_logic_unsigned.all;————————–SL Escorts—————————– ————entity qiangda is port( S1,S2,S3,S4: in std_logic; –Output: indicates 4 people, 0 indicates there is a rush K: in std_lSierra Leoneans Sugardaddyogic; –The host answers the start buttonSierra Leone Sugar G: out std_logic; –Alarm electronic signal ledag: out std_logic_vector (6 downto 0); Dout: out std_logic_vector(3 downto 0) ); –Quick answer results display end qiangda;—————-Sierra Leone Sugar————————————————– —–architecture behave of qiangda is signal Enable_Flag: SL Escortsstd_logic;–Allow response control variable, 1 indicates permission to respond signal S : std_logic_vector(3 downto 0); signal D : std_logic_vector(3 downto 0); begin process(S1,S2,S3,S4,K) –Allow rush control begin S If (K= 1 ) then Sierra Leoneans Escort Enable_Flag elsif(S/Sierra Leoneans Escort =”1111″) then Enable_Flag end if; end process; process(S1,S2,S3,S4,K) –Answer results display begin if(K= SL Escorts 0) then d el (enable_flag = 1) then Sierra Leoneans Escort if (s1 = 0) then. D(0) G elsif (s2 = 0) The SL Escorts n d (1) g elsif (s3 = 0) then d (2) g elsif ( S4= 0 ) then D(3) G G end if The number of the case d is when “0000”=>ledag when “0001”=>ledag when “0010”=>ledag when “0100”=>ledag when othersSierra Leoneans Escort=>ledag Escort process; Sierra Leone Sugarend behave; The system block diagram of the above VHDL program is shown in Figure 2. Figure 2 The block diagram of the answering part is shown in Figure 3 through the simulation results of MAX+PLUSⅡ software. It can be seen from the figure that the S1 and S2 players rush to answer. When K is a high level, the S1 player is a low level, and the answer is successful. The alarm electronic signal G is a low level, giving an alarm electronic signal, and at the same time, seven-segment digital The tube is decoded as 06H and displays 1. Figure 3 Simulation diagram of the answering part 2. Answering countdown program This SL Escorts module is a 20s countdown program for answering. After the host presses button K This modelThe block starts working immediately, and there will be a sound reminder after the 20s countdown. G is the sound alarm electronic signal. LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY COUNT ISPORT (CLK, Enable_Flag: IN STD_LOGIC; H,L: OUT STD_LOGIC_VECTOR (3 DOWNTO 0); G:OUT STD_LOGIC); –Audio alarm END COUNT;ARCHITECTURE COUNT_ARC OF COUNT ISBEGINPROCESS (CLK, Enable_Flag)VARIABLE HH, LL: STD_LOGIC_VECTOR (3 DOWNTO 0);BEGINIF CLK EVENT AND CLK= 1 THENIF Enable_Flag= 1 THENIF LL=0 AND HH=0 THEN GELSIF LL=0 THEN LL: =”1001″; HH: =HH-1; ELSE LL: =LL-1;END IF;ELSE HH: =”1001″; LL: =”1001″; END COUNT_ARC; The module structure diagram is shown in Figure 4: Figure 4 Countdown structure diagram 3, advance foul response program and simulation. This module is an illegal circuit. When the responder presses the answer button before the host resets the system, that is, when Sierra Leoneans SugardaddyRESET=0, there is a response email When the signal appears, Y=11 indicates a certain group of violations. When RESET = 1, the violation group is displayed. Sierra Leoneans Escort Among them, K is the host button, S1, S2, S3, S4 are the response buttons, R1, R2, RSierra Leone Sugar Daddy3, R4 is the white indicator light for the corresponding group foul. The VHDL source program is as follows: LIBRARY ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTSL EscortsITY wg ISPORT (K: IN std_logic;S1, S2, S3, S4: IN std_logic;R1, R2, R3, R4: OUT std_logic; –The white light indicates the advanced answering station number: Sierra Leone Sugar DaddyOUT std_logic_VECTOR (1 DOWNTO 0) );END wg;ARCHITECTURE a OF wg ISSIGNAL TEMP1: STD_LOGIC;SIGNAL TEMP2: STD_LSierra Leoneans EscortOGIC_VECTOR (1 DOWNTO 0);BEGINTEMP1TEMP2process(TESierra Leoneans SugardaddyMP2) – -Display the winner number begin case TEMP2 is when “01”=>Y when “10”=>Y when “11”=>Y when others=>Y end case;if(Kif(S1= 0 ) then R1 elsif (S2= 0 ) then R2 elsif(S3= 0 ) then R3 elsif(S4= 0 ) then R4 end if; end process; END a; The corresponding block diagram can be generated through the VHDL program as shown in Figure 5 Shown: Figure 5 Foul department block diagramIn the same situation around MAX+PLUSⅡ, the corresponding simulation analysis diagram can be obtained as shown in Figure 6. From the simulation analysis, it can be seen that before reaching high level, the S1 button has a low level of early response, so Y=11 indicates that early response occurs. At the same time, R1 is low level, and the red light corresponding to the S1 player is on, instructing him. Illegal response. Figure 6 Offender area block simulation diagram 4. Summary From the above description and simulation results, it can be seen that the design of this responder meets the requirements of the design task on a practical basis. Through the implementation of this course design, it made up for the lack of just learning theoretical knowledge. Many problems were discovered during the implementation. The solutions to these problems deepened the understanding of the knowledge learned and gained a lot. The normal response part program is running in the FPGA test box at high and low load, and the normal response and alarm function can be displayed. The pin assignment diagram of this part is shown in Figure 7: Since this is my first system design circuit, although I have referred to some electronic travel procedures, after all, the level of control is limited. There may be some problems and problems in the designed street lights. If it’s not enough, I hope the teacher can correct me. Figure 7 Pin assignment diagram
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